<b>Semiconductor package</b> and method for fabricating the same

US10629522B2 · office US · priority 2017-02-08 · published 2020-04-21

6. The semiconductor package of claim 1 , further comprising an additional dielectric layer disposed on a surface of the first redistribution layer opposite the first molding compound, wherein the conductive vias extend through the additional dielectric layer. 7. The semiconductor package of claim 6

Inventor: Shing-Yih Shih · Assignee: Micron Technology, Inc.

Open the patent document · source query “US/semiconductor packaging”